Phase locked loops (PLL) are widely used in various applications such as wireless communication system and wireline communication system. The PLL is a closed-loop feedback control system that generates a signal in relation to the frequency and phase of a reference signal. PLL may be implemented as either analog or digital circuits including a phase detector (PD), a loop filter (LF), a voltage controlled oscillator (VCO), and a feedback path. The PLL may also include a frequency divider in a feedback configuration between the VCO and the PD. In some applications it may be desirable to output a frequency that is a fractional multiple of the reference signal. In this situation, a fractional PLL is necessary to divide the output frequency of the VCO by a fractional number.
Various techniques are used to implement a fractional PLL frequency divider. One such technique is adopting a multi modulus divider. A modulator may be used to drive the multi modulus divider with different integer division factors in order to obtain a fractional average division factor. However, fractional spurs may be generated in a fractional PLL. The modulator used to control the frequency divider may introduce noise into PLL. Nonlinearity of several blocks in PLL, such as integer frequency divider, phase detector, charge pump and loop filter may cause fractional spurs. Thus there is a need for a PLL having a fractional frequency divider insensitive to nonlinearity effect.